ExaFPGA aims at accelerating a limited class of algorithms (namely: static affine nested loops - SANLP - and iterative stencil loops - ISL) using FPGAs. This project provides a complete methodology that enables designers to write C code, mark the computational SANLP/ISL kernel, analyze it and distribute the workload onto a set of available FPGA-based accelerators.
This is an actively developed project for which we offer numerous thesis proposals in the computer architecture, compilers, languages and operating systems areas; in case you are interested, feel free to visit the project's website . As a plus, we have biscuits in the lab :P
Imagine a revolutionary computing system that can observe its own execution and optimize its behavior with respect to the external environment, to the user and to the applications demands. Provide users with the possibility to specify their desired goals along with constraints in terms of energy budget, time, and computational accuracy. Design a computing chip performing better, according to a set of goals expressed by the user, the longer it runs an application. The full range of computing infrastructures, from embedded devices to personal computer to servers to supercomputers, would benefit from the adoption of this technology. This research focuses on building a Self-Aware Reconfigurable Computing System to fulfill the vision above. This system is given a goal and a budget – it then finds the best way to accomplish the goal despite changes in both the available resources and the environment. A self-aware system has cognitive mechanisms in its trusted components to both observe and to affect the execution. Since it is impossible to pre-configure all possible scenarios, these systems also implement learning and decision making engines in a judicious combination of hardware and software to determine the appropriate actions based on given observations. To achieve the vision just described, a Self-Aware Reconfigurable computing system is no longer viewed as a static bunch of hardware components with a passive set of applications running on top of an operating system, which properly coordinates the underling architecture. It becomes an active system where the hardware, the applications and the operating system are seen as a unique entity. This entity needs to adapt itself to guarantee the goal(s) achievement. Starting from the joint research of Politecnico di Milano and MIT, people at UIC and Harvard joined the community, broadening the group expertise.
FASTER is an european project that aims to facilitate the use of reconfigurable technology by providing a complete methodology that enables designers to easily implement and verify applications on platforms with general-purpose processors and acceleration modules implemented in the latest reconfigurable technology. Reconfigurable logic allows the definition of new functions to be implemented in dynamically instantiated hardware units, combining adaptivity with hardware speed and efficiency. This project is financed by European Commision.