Hello!
I am a PhD Student at Dipartimento di Elettronica e Informazione, Politecnico di Milano in Italy, working at NECSTLab with Marco D. Santambrogio. My research interests revolve around automatic acceleration of scientific workloads onto FPGA-based supercomputers.
Contacts
Email riccardo.cattaneo@polimi.itNECST Laboratory
Dipartimento di Elettronica ed Informazione
Politecnico di Milano
Via Ponzio 34/5, Milano (MI) 20133, Italy
Phone: +39 02 23993564 Social
Research
Research Projects
Active projects- exaFPGA
- FASTER (EU FP7)
- EXTRA (EU H2020)
Short Bio
Riccardo Cattaneo received his Bachelor and Master degrees in Computer Engineering from the Politecnico di Milano in Febraury 2010 and April 2012. He also received a Master of Science in Computer Science from University of Illinois in Chicago in 2012. His research interests revolve around automatic acceleration of scientific workloads onto FPGA-based supercomputers. Specifically, his PhD major targets the specification and development of a system level design tool able to automatically accelerate a C-based computationally-intesive program onto an FPGA-based supercomputing platform, exaFPGA. He is (and was) involved in multiple research projects funded by EU, like FASTER and EXTRA.
Selected Publications
On how to Accelerate Iterative Stencil Loops: A Scalable Streaming-based Approach
R. CATTANEO, G. Natale, C. Sicignano, D. Sciuto, M. D. Santambrogio
ACM Transactions on Architecture and Code Optimization (TACO)
View moreExplicitly Isolating Data and Computation in High Level Synthesis: the Role of Polyhedral Framework
R. CATTANEO, G. Pallotta, D.Sciuto, M. D. Santambrogio
International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2015
